1. Field of the Invention
The present invention relates to an LCD device, and more particularly, to a circuit and method for driving an LCD device, which is capable of reducing power consumption of the LCD device.
2. Discussion of the Related Art
Generally, a liquid crystal display (LCD) panel includes two plates facing each other, and an LC layer with dielectric anisotropy characteristic between the two plates.
An LCD device including an LCD panel is operated such that, in a state where a voltage is applied to the LC layer, as intensity of electric fields formed by the voltage is controlled to adjust transmittance of light passing through the LC layer, desired images can be displayed thereon. The LCD device is a typical example of flat panel display (FPD) which can be easily carried. Most of LCD devices adopt a TFT-LCD panel which is implemented with thin film transistors (TFT) as a switching element, which is hereinafter referred to as a TFT-LCD device.
The TFT-LCD panel includes a plurality of gate lines for transmitting scan signals thereto, and a plurality of data lines for transmitting image data thereto. The data lines are formed by orthogonally crossing with the gate liens to define a plurality of pixels enclosed thereby. Namely, pixels are formed in a matrix type. Each pixel is connected to a gate line and a data line through a TFT.
In order to apply image signal to each pixel of the LCD device, a scan signal is sequentially applied to the gate lines such that the TFTs connected to the gate lines can be sequentially turned on, and, at the same time, an image signal (i.e., a gray level voltage), which will be applied to a row of pixels corresponding to the gate line, is applied to each data line. The image signal applied to the data line is applied to each pixel through the turned-on TFTs. Here, the gate ON signal is sequentially applied to all gate lines such that the image signal can be applied to all rows of pixels, for one frame period. Therefore, one frame of image is displayed on the LCD panel.
The gray level voltage applied to the data line of the LCD device is a voltage applied to the source of the TFT to generate gray levels. The gray levels of a color TFT-LCD device are determines by the bit number of Red-, Green- and Blue-data which are outputted from a graphic controller. For example, when Red-data of 6 bits are inputted, 64 (26) gray levels are formed such that a red can be expressed by 64 gray levels.
In order to express 64 gray levels, 64 gray level voltages are needed. For example, the voltage range between 0˜10V (in case of high voltage drive) is equally divided into 64 steps, and then the voltages of the 64 steps are provided to the data driver. However, when the data driver has generates 8-divided voltages, it can be operated only if 9 gray level voltages are inputted to the data driver from the outside. Therefore, 9 gray level voltages are required such that the range of 0˜10V can be divided into 8 steps. The above-described method for generating gray level voltages uses a voltage divider using a plurality of resistors.
The voltages divided by each resistor (hereinafter referred to as ‘gray level voltage’) serves to express the gray levels which are provided to the data lines according to the selection of the data signals. On the other hand, the resistor array (voltage divider) has disadvantages in that the greater the number of gray levels the greater the number of resistors is required. In order to resolve such a problem, a hybrid driving circuit using resistors and capacitors has been developed.
The related art hybrid driving circuit includes: a gray level voltage generator for generating a plurality of gray level voltages corresponding to the data of a part of bits among the data of N bits (N is a positive integer) for displaying images; a decoder unit for selecting and outputting two gray level voltages (hereinafter referred to as first and second gray level voltages) among the plurality of gray level voltages according to the data of a part of bits; a switching signal generator for combining data of the remaining bits among the data of N bits with control signals outputted from the outside and for generating a plurality of switching signals based on the combination result; and an intermediate gray level voltage generator for receiving the first and second gray level voltages from the decoder unit, for generating a third gray level voltage, whose value is between values of the first and second gray level voltages, and for selectively outputting the first or third gray level voltage according to the switching signals.
The intermediate gray level voltage generator receives the first and second gray level voltages from the decoder unit. The intermediate gray level voltage generator reads out a logic value of the least significant bit of the N bits data and outputs the first or third gray level voltage based on the readout result. Namely, when the logic value of the least significant bit is ‘0,’ the intermediate gray level voltage generator outputs the first gray level voltage. On the other hand, when the logic value is ‘1,’ the intermediate gray level voltage generator outputs the third gray level voltage.
The gray level voltage generator generates, for example, 32 gray levels of the total gray levels (for example, 64 gray levels). Also, the intermediate gray level voltage generator receives two adjacent gray level voltages and generates a third gray level voltage between the two adjacent gray level voltages.
More specifically, the intermediate gray level voltage generator will be described in detail below, referring to FIG. 1. FIG. 1 illustrates a circuit of an intermediate gray level voltage generator in a related art hybrid-type circuit for driving an LCD device. As shown in FIG. 1, the intermediate gray level voltage generator 103 includes an operational amplifier AMP, first and second capacitors CAP1 and CAP2, and 1st-5th switches SW1-SW5.
One end of the 1st switch SW1 is connected to a first input lead 201 to which a first gray level voltage Vrl is provided. One end of the 2nd switch SW2 is connected to a second input lead 202 to which a second gray level voltage Vrh is provided. Each of the other end of the 1st and 2nd switches SW1 and SW2 is connected to a first node n1. The first capacitor CAP1 is located between the first node 1 and the inverting lead (−) of the operational amplifier AMP. The 3rd and 4th switches SW3 and SW4 are serially located between the first node n1 and the output lead 203 of the operational amplifier AMP. The second capacitor CAP2 and the 5th switch SW5 are serially located between a second node n2, which is between the 3rd and 4th switches SW3 and SW4, and the output lead 203 of the operational amplifier AMP. The inverting lead (−) of the operational amplifier AMP is connected to a third node n3 between the second capacitor CAP2 and the 5th switch SW5. The non-inverting lead (+) of the operational amplifier AMP is connected to a third input lead 204 to which a reference voltage Vref is provided.
Here, the 1st-5th switches SW1-SW5 are turned on or turned off according to the switching signals of the switching signal generator (not shown). In reference, the switching signal generator is not always necessary. Namely, the intermediate gray level voltage generator can be controlled by other units providing the switch signal not by the switching signal generator. The intermediate gray level voltage generator 103 selectively turns on or off the 1st-5th switches SW1-SW5 according to the switching signals, such that one of the first gray level voltage Vrl and the third gray level voltage can be outputted to the output lead 203 of the operational amplifier AMP. Here, the magnitude of the third gray level voltage is determined by capacitances of the first and second capacitors CAP1 and CAP2.
As described above, the related art hybrid circuit for driving an LCD device reduces the number of resistors R as some of gray level voltages among the total gray level voltages are generated through the resistors of the gray level voltage generator and the remaining gray level voltages are generated by the capacitors CAP1 and CAP2 included in the intermediate gray level voltage generator 103. However, the related art circuit has disadvantages in that it must be configured such that the gray level voltage generator must provide a relatively high driving current to charge the capacitors CAP1 and CAP2, and the operational amplifier does not involve in charging the capacitors CAP1 and CAP2. Therefore, the power consumption of the gray level voltage generator is increased.